IBM POWER6 microarchitecture

microarchitecture H. Q. Le W. J. Starke J. S. Fields F. P. O’Connell D. Q. Nguyen B. J. Ronchetti W. M. Sauer E. M. Schwarz M. T. Vaden This paper describes the implementation of the IBM POWER6e microprocessor, a two-way simultaneous multithreaded (SMT) dual-core chip whose key features include binary compatibility with IBM POWER5e microprocessor-based systems; increased functional capabilities, such as decimal floating-point and vector multimedia extensions; significant reliability, availability, and serviceability enhancements; and robust scalability with up to 64 physical processors. Based on a new industry-leading highfrequency core architecture with enhanced SMT and driven by a high-throughput symmetric multiprocessing (SMP) cache and memory subsystem, the POWER6 chip achieves a significant performance boost compared with its predecessor, the POWER5 chip. Key extensions to the coherence protocol enable POWER6 microprocessor-based systems to achieve better SMP scalability while enabling reductions in system packaging complexity and cost.